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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16782
SOURCE DRIVER FOR 300/288-OUTPUT TFT-LCD (NAVIGATION, AUTOMOBILE LCD-TV)
DESCRIPTION
PD16782 is a source driver for TFT liquid crystal panels. This IC consists of a multiplexer circuit supporting a variety of
pixel arrays, a shift register that generates sampling timing, and two sample and hold circuits that sample analog voltages. Because the two sample and hold circuits alternately execute sampling and holding, a high definition can be obtained. In addition, simultaneous sampling and successive sampling are automatically selected according to the pixel array of the LCD panel. It is ideal for a wide range of applications, including navigation systems and automobile LCD-TVs.
FEATURES
* Can be driven on 5 V (Dynamic range: 4.3 V, VDD2 = 5.0 V) * 300/288-output * fCLK = 15 MHz MAX. (VDD1 = 3.0 V) * Simultaneous/successive sampling selectable according to pixel array Simultaneous sampling: Vertical stripe Successive sampling: Delta array, mosaic array * Two sample and hold circuits * Low output deviation between pins ( 20 mV MAX.) * Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit * Left and right shift selected by R,/L pin * COG mounting possible
Remark /xxx indicates active low signal.
ORDERING INFORMATION
Part Number Package Chip
PD16782P
Remark
Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
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Document No. S15806EJ1V0DS00 (1st edition) Date Published December 2002 NS CP (K) Printed in Japan
2001
PD16782
1. BLOCK DIAGRAM
STHR R,/L CLI1~CLI3 INH Osel C1 C2 C3
300-bit bidirectional shift register
STHL VDD1 VSS1
C299 C300
Level shifter
RESET
C1 C2 C3
VDD2 Multiplexer Sample and Hold VSS2
MP/TH MP/1.5 S1 S2 S3 S300
(monitor) RMON1, RMON2
2. SAMPLE AND HOLD CIRCUIT AND OUTPUT CIRCUIT
+
Swa1 Video Line CH1
Swb1 Sn
+
Swa2 CH2
Swb2
2
Data Sheet S15806EJ1V0DS
PD16782
3. PIN CONFIGURATION
VSS2
Alignment mark: (50 x 50 m2 ) Output dummy pin
S300 S299 S298
Input dummy pin
RMON1 RMON1
Connected resistance measurement pin
VDD2
VSS1
VDD1
C1
C2
C3
STHL
MP/TH MP/1.5 R,/L RESET INH CLI1 CLI2 CLI3 TEST STHR 0 X(+) Y(+)
Osel VDD1
VSS1
VDD2
Connected resistance measurement pin
RMON2 RMON2 S2 S1
Input dummy pin
VSS2
Output dummy pin Alignment mark: (50 x 50 m 2 )
Data Sheet S15806EJ1V0DS
3
PD16782
Table 3-1. Pad Layout (1/4) -
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 PAD Name Dummy1 RMON1 RMON1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 C1 C1 C1 C1 C1 C1 C2 C2 C2 C2 C2 C2 C3 C3 C3 C3 C3 C3 STHL STHL STHL STHL STHL STHL MP/TH MP/TH X [m] -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 Y [m] 8451.0 8014.2 7842.0 7538.6 7458.6 7378.6 7298.6 7218.6 7138.6 7058.6 6978.6 6898.6 6818.6 6738.6 6658.6 6181.0 6101.0 6021.0 5941.0 5861.0 5781.0 5701.0 5239.4 5159.4 5079.4 4999.4 4919.4 4839.4 4759.4 4335.2 4255.2 4175.2 4095.2 4015.2 3935.2 3470.4 3390.4 3310.4 3230.4 3150.4 3070.4 2605.6 2525.6 2445.6 2365.6 2285.6 2205.6 1384.2 1304.2 1224.2 1144.2 1064.2 984.2 538.6 458.6 Bump Size (X:Y) [m] 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 No. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 PAD Name MP/TH MP/1.5 MP/1.5 MP/1.5 R,/L R,/L R,/L RESET RESET RESET INH INH INH CLI1 CLI1 CLI1 CLI2 CLI2 CLI2 CLI3 CLI3 CLI3 TEST TEST TEST STHR STHR STHR STHR STHR STHR Osel Osel Osel VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 X [m] -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 Y [m] 378.6 145.5 65.5 -14.5 -247.6 -327.6 -407.6 -640.7 -720.7 -800.7 -1033.8 -1113.8 -1193.8 -1427.0 -1507.0 -1587.0 -1820.1 -1900.1 -1980.1 -2213.2 -2293.2 -2373.2 -2606.3 -2686.3 -2766.3 -3227.0 -3307.0 -3387.0 -3467.0 -3547.0 -3627.0 -4170.4 -4250.4 -4330.4 -4759.4 -4839.4 -4919.4 -4999.4 -5079.4 -5159.4 -5239.4 -5701.0 -5781.0 -5861.0 -5941.0 -6021.0 -6101.0 -6181.0 -6658.6 -6738.6 -6818.6 -6898.6 -6978.6 -7058.6 -7138.6 Bump Size (X:Y) [m] 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60
4
Data Sheet S15806EJ1V0DS
PD16782
Table 3-1. Pad Layout (2/4) -
No. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 PAD Name VDD2 VDD2 VDD2 VDD2 VDD2 RMON2 RMON2 Dummy2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 Dummy3 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 X [m] -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -464.0 -399.8 -319.8 -239.8 -159.8 -79.8 0.2 80.2 160.2 240.2 320.2 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 Y [m] -7218.6 -7298.6 -7378.6 -7458.6 -7538.6 -7842.0 -8014.2 -8451.0 -8769.0 -8769.0 -8769.0 -8769.0 -8769.0 -8769.0 -8769.0 -8769.0 -8769.0 -8769.0 -8642.5 -8585.5 -8528.5 -8471.5 -8414.5 -8357.5 -8300.5 -8243.5 -8186.5 -8129.5 -8072.5 -8015.5 -7958.5 -7901.5 -7844.5 -7787.5 -7730.5 -7673.5 -7616.5 -7559.5 -7502.5 -7445.5 -7388.5 -7331.5 -7274.5 -7217.5 -7160.5 -7103.5 -7046.5 -6989.5 -6932.5 -6875.5 -6818.5 -6761.5 -6704.5 -6647.5 -6590.5 Bump Size (X:Y) [m] 100:60 100:60 100:60 100:60 100:60 100:60 100:60 100:60 60 100 60 100 60 100 60 100 60 100 60 100 60 100 60 100 60 100 60 100 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 No. 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 PAD Name S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 X [m] 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 Y [m] -6533.5 -6476.5 -6419.5 -6362.5 -6305.5 -6248.5 -6191.5 -6134.5 -6077.5 -6020.5 -5963.5 -5906.5 -5849.5 -5792.5 -5735.5 -5678.5 -5621.5 -5564.5 -5507.5 -5450.5 -5393.5 -5336.5 -5279.5 -5222.5 -5165.5 -5108.5 -5051.5 -4994.5 -4937.5 -4880.5 -4823.5 -4766.5 -4709.5 -4652.5 -4595.5 -4538.5 -4481.5 -4424.5 -4367.5 -4310.5 -4253.5 -4196.5 -4139.5 -4082.5 -4025.5 -3968.5 -3911.5 -3854.5 -3797.5 -3740.5 -3683.5 -3626.5 -3569.5 -3512.5 -3455.5 Bump Size (X:Y) [m] 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37
Data Sheet S15806EJ1V0DS
5
PD16782
Table 3-1. Pad Layout (3/4) -
No. 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 PAD Name S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 X [m] 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 Y [m] -3398.5 -3341.5 -3284.5 -3227.5 -3170.5 -3113.5 -3056.5 -2999.5 -2942.5 -2885.5 -2828.5 -2771.5 -2714.5 -2657.5 -2600.5 -2543.5 -2486.5 -2429.5 -2372.5 -2315.5 -2285.5 -2201.5 -2144.5 -2087.5 -2030.5 -1973.5 -1916.5 -1859.5 -1802.5 -1745.5 -1688.5 -1631.5 -1574.5 -1517.5 -1460.5 -1403.5 -1346.5 -1289.5 -1232.5 -1175.5 -1118.5 -1061.5 -1004.5 -947.5 -890.5 -833.5 -776.5 -719.5 -662.5 -605.5 -548.5 -491.5 -434.5 -377.5 -320.5 Bump Size (X:Y) [m] 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 No. 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 PAD Name S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S159 S160 S161 S162 S163 S164 S165 S166 S167 S168 S169 S170 S171 S172 S173 S174 S175 S176 S177 S178 S179 S180 S181 S182 S183 S184 S185 S186 S187 S188 S189 S190 S191 S192 S193 S194 S195 S196 S197 S198 S199 S200 S201 X [m] 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 Y [m] -263.5 -206.5 -149.5 -92.5 -35.5 21.5 78.5 135.5 192.5 249.5 306.5 363.5 420.5 477.5 534.5 591.5 648.5 705.5 762.5 819.5 876.5 933.5 990.5 1047.5 1104.5 1161.5 1218.5 1275.5 1332.5 1389.5 1446.5 1503.5 1560.5 1617.5 1674.5 1731.5 1788.5 1845.5 1902.5 1959.5 2016.5 2073.5 2130.5 2187.5 2244.5 2301.5 2358.5 2415.5 2472.5 2529.5 2586.5 2643.5 2700.5 2757.5 2814.5 Bump Size (X:Y) [m] 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37
6
Data Sheet S15806EJ1V0DS
PD16782
Table 3-1. Pad Layout (4/4) -
No. 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 PAD Name S202 S203 S204 S205 S206 S207 S208 S209 S210 S211 S212 S213 S214 S215 S216 S217 S218 S219 S220 S221 S222 S223 S224 S225 S226 S227 S228 S229 S230 S231 S232 S233 S234 S235 S236 S237 S238 S239 S240 S241 S242 S243 S244 S245 S246 S247 S248 S249 S250 S251 S252 S253 S254 S255 S256 X [m] 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 Y [m] 2871.5 2928.5 2985.5 3042.5 3099.5 3156.5 3213.5 3270.5 3327.5 3384.5 3441.5 3498.5 3555.5 3612.5 3669.5 3726.5 3783.5 3840.5 3897.5 3954.5 4011.5 4068.5 4125.5 4128.5 4239.5 4296.5 4353.5 4410.5 4467.5 4524.5 4581.5 4638.5 4695.5 4752.5 4809.5 4866.5 4923.5 4980.5 5037.5 5094.5 5151.5 5208.5 5265.5 5322.5 5379.5 5436.5 5493.5 5550.5 5607.5 5664.5 5721.5 5778.5 5835.5 5892.5 5949.5 Bump Size (X:Y) [m] 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 No. 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 PAD Name S257 S258 S259 S260 S261 S262 S263 S264 S265 S266 S267 S268 S269 S270 S271 S272 S273 S274 S275 S276 S277 S278 S279 S280 S281 S282 S283 S284 S285 S286 S287 S288 S289 S290 S291 S292 S293 S294 S295 S296 S297 S298 S299 S300 Dummy4 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 Alignment mark 1 Alignment mark 2 X [m] 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 402.0 320.2 240.2 160.2 80.2 0.2 -79.8 -159.8 -239.8 -319.8 -399.8 429.2 429.2 Y [m] 6006.5 6063.5 6120.5 6177.5 6234.5 6291.5 6348.5 6405.5 6462.5 6519.5 6576.5 6633.5 6690.5 6747.5 6804.5 6861.5 6918.5 6975.5 7032.5 7089.5 7146.5 7203.5 7260.5 7317.5 7374.5 7431.5 7488.5 7545.5 7602.5 7659.5 7716.5 7773.5 7830.5 7887.5 7944.5 8001.5 8058.5 8115.5 8172.5 8229.5 8286.5 8343.5 8400.5 8457.5 8514.5 8769.0 8769.0 8769.0 8769.0 8769.0 8769.0 8769.0 8769.0 8769.0 8769.0 8779.8 -8779.8 Bump Size (X:Y) [m] 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 80:37 60:100 60:100 60:100 60:100 60:100 60:100 60:100 60:100 60:100 60:100
Data Sheet S15806EJ1V0DS
7
PD16782
4. PIN FUNCTIONS
Symbol C1 to C3 S1 to S300 STHR, STHL CLI1 to CLI3 Pin Name Video signal input Video signal output Cascade I/O Pad No. 30 to 47 130 to 429 81 to 86, 48 to 53 69 to 77 I/O Input Output I/O Description Input R, G, and B video signals. Video signal output pins. Output sampled and held video signals during horizontal period. Start pulse I/O pins of sample hold timing. STHR serves as an input pin and STHL, as an output pin, in the case of right shift. In the case of left shift, STHL serves as an input pin, and STHR, as an output pin. A start pulse is read at the rising edge of CLI1. Sampling pulse SHPn is generated at the rising edge of CLI1 through CLI3 during successive sampling, and at the rising edge of CLI1 during simultaneous sampling (for details, refer to the Timing charts in 5. FUNCTIONAL DESCRIPTION). Selects a multiplexer and one of the two sample and hold circuits at the falling edge. Resets the select counter of the multiplexer and the selector circuit of the two sample and hold circuits when it goes high. After reset, the multiplexer is turned OFF, so sure to input one pulse of the INH signal before inputting the video signal. If the video signal is input without the INH signal, sampling is not executed. Four types of color filter arrays can be supported by combination of MP/TH and MP/1.5. Mode Vertical stripe array MP/1.5 Multiplexer circuit select input (2) 57 to 59 Input Single-side delta array Mosaic array Double-side delta array MP/TH L L H H MP/1.5 L H L H
Shift clock input
Input
INH RESET
Inhibit input Reset input
66 to 68 63 to 65
Input Input
MP/TH
Multiplexer circuit select input (1)
54 to 56
Input
R,/L Osel
Shift direction select input Selection of Number of outputs switching input
60 to 62 87 to 89
Input Input
R,/L = H: Right shift: STHR S1 S300 STHL R,/L = L: Left shift: STHL S300 S1 STHR Selects number of outputs. Osel = L: 288 output mode Osel = H: 300 output mode Output pins S145 through S156 are invalid in 288 output mode. The signal which is with S157 to S168 (R,/L = H) or S133 to S144 (R,/L = L) is output identically. This pin can measure the connection resistance at the time of COG mounting. RMON1 and RMON2 are each short inside IC. It does not connect with other pins inside IC. No dummy pins are connected with other pins inside IC. 3.0 to 5.5 V 5.0 0.5 V Connect this pin to ground of system. Connect this pin to ground of system. Fix this pin to low level.
RMON1, RMON2 Dummy1 to Dummy4 VDD1 VDD2 VSS1 VSS2 TEST
Monitor
2, 3, 116, 117 1, 118, 129, 430 23 to 29, 90 to 96 4 to 15, 104 to 115 16 to 22, 97 to 103 119 to 128, 431 to 440 78 to 80
Dummy Logic power supply Driver power supply Logic ground Driver ground Test
8
Data Sheet S15806EJ1V0DS
PD16782
5. FUNCTIONAL DESCRIPTION
5.1 Multiplexer Circuit This circuit selects RGB video signals input to the C1 to C3 pins according to the pixel array of the liquid crystal panel, and outputs the signals to the S1 through S300 pins. Vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the MP/TH and MP/1.5 pins. 5.1.1 Vertical stripe array mode (MP/TH = L, MP/1.5 = L) In this mode, the relation between video signals C1 to C3, and output pins is as shown below. This mode is used to drive a panel of vertical stripe array. In this mode, the multiplexer circuit is in the through status. Table 5-1. Relation between Video Signals C1 to C3, and Output Pins (during right shift) -
Line No. (number of INHs) 0 1 2 3 : RESET INH S1 to S300 Sampling C1 (C3) Output C1 (C3) Output C1 (C3) Output C1 (C3) : S2 to S299 Sampling C2 (C2) Output C2 (C2) Output C2 (C2) Output C2 (C2) : S3 to S298 Sampling C3 (C1) Output C3 (C1) Output C3 (C1) Output C3 (C1) : S4 to S297 Sampling C1 (C3) Output C1 (C3) Output C1 (C3) Output C1 (C3) : ... ... ... ... ... ... S299 to S2 Sampling C2 (C2) Output C2 (C2) Output C2 (C2) Output C2 (C2) : S300 to S1 Sampling C3 (C1) Output C3 (C1) Output C3 (C1) Output C3 (C1) :
H L L L :
L :
Remark ( ) indicates the case of left shift. Figure 5-1. Pixel Arrangement of Vertical Stripe Array and Multiplexer Operation -
R B G C1 C2 C3
PD16782 S1 S2
Right shift (R,/L = "H"), MP/TH = "L", MP/1.5 = "L" S3 S4 S5 S6 S7
R R R R R
B B B B B
G G G G G
R R R R R
B B B B B
G G G G G
R R R R R
Data Sheet S15806EJ1V0DS
9
PD16782
Figure 5-2. Timing Chart of Vertical Stripe Array -
RESET INH S1 (S300) Sampling input data Output S2 (S299) Sampling input data Output S3 (S298) Sampling inputdata Output undifined
C1 (C3)
C1 (C3) C1 (C3)
C1 (C3) C1 (C3)
C1 (C3) C1 (C3)
C1 (C3) C1 (C3) C1 (C3)
undifined
undifined
C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2) C2 (C2)
undifined
undifined
C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1) C3 (C1)
undifined
S299 (S2) Sampling input data Output S300 (S1) Sampling input data Output
undifined
C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2)
C2 (C2) C2 (C2) C2 (C2)
undifined
undifined
C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1)
C3 (C1) C3 (C1) C3 (C1)
undifined
10
Data Sheet S15806EJ1V0DS
PD16782
5.1.2 Single-side delta array mode (MP/TH = L, MP/1.5 = H) Table 5-2. Relation between Video Signals C1 to C3, and Output Pins -
Line No. (number of INHs) 0 1 2 3 4 5 : RESET INH S1 to S300 S2 to S299 S3 to S298 S4 to S297 ... ... ... ... ... ... S299 to S2 S300 to S1
H L L L L L :
L :
Undefined Sampling C1 (C3) Output C1 (C3) Output C2 (C1) Output C1 (C3) Output C2 (C1) :
Undefined Sampling C2 (C2) Output C2 (C2) Output C3 (C3) Output C2 (C2) Output C3 (C3) :
Undefined Sampling C3 (C1) Output C3 (C1) Output C1 (C2) Output C3 (C1) Output C1 (C2) :
Undefined Sampling C1 (C3) Output C1 (C3) Output C2 (C1) Output C1 (C3) Output C2 (C1) :
Undefined Sampling C2 (C2) Output C2 (C2) Output C3 (C3) Output C2 (C2) Output C3 (C3)
Undefined Sampling C3 (C1) Output C3 (C1) Output C1 (C2) Output C3 (C1) Output C1 (C2) :
...
:
Remark ( ) indicates the case of left shift. Figure 5-3. Pixel Arrangement of Single-Side Delta Array and Multiplexer Operation -
R B G C1 C2 C3
PD16782 S1 S2
Right shift (R,/L = "H"), MP/TH = "L", MP/1.5 = "H" S3 S4 S5 S6 S7
R B R B R B R G G G
B R B R B R B
G B G B G B G
R G R G R G R
B R B R B R B
G B G B G B G
R G R G R G R
Data Sheet S15806EJ1V0DS
11
PD16782
Figure 5-4. Timing Chart of Single-Side Delta Array -
RESET INH S1 (S300) Sampling input data Output S2 (S299) Sampling input data Output S3 (S298) Sampling inputdata Output undifined
undifined
C1 (C3)
undifined
C2 (C1) C1 (C3)
C1 (C3) C2 (C1)
C2 (C1) C1 (C3) C2 (C1)
undifined
undifined
undifined
C2 (C2)
undifined
C3 (C3) C2 (C2)
C2 (C2) C3 (C3)
C3 (C3) C2 (C2) C3 (C3)
undifined
undifined
undifined
C3 (C1)
undifined
C1 (C2) C3 (C1)
C3 (C1) C1 (C2)
C1 (C2) C3 (C1) C1 (C2)
undifined
S299 (S2) Sampling input data Output S300 (S1) Sampling input data Output
undifined
undifined
C2 (C2)
undifined
C3 (C3) C2 (C2)
C2 (C2) C3 (C3)
C3 (C3) C2 (C2) C3 (C3)
undifined
undifined
undifined
C3 (C1)
undifined
C1 (C2) C3 (C1)
C3 (C1) C1 (C2)
C1 (C2) C3 (C1) C1 (C2)
undifined
12
Data Sheet S15806EJ1V0DS
PD16782
5.1.3 Double-side delta array mode (MP/TH = H, MP/1.5 = H) Table 5-3. Relation between Video Signals C1 to C3 and Output Pins -
Line No. (number of INHs) 0 1 2 3 4 5 : RESET INH S1 to S300 S2 to S299 S3 to S298 S4 to S297 ... ... ... ... ... ... ... ... S299 to S2 S300 to S1
H L L L L L :
L :
Undefined Sampling C2 (C3) Output C2 (C3) Output C1 (C1) Output C2 (C3) Output C1 (C1) :
Undefined Sampling C3 (C2) Output C3 (C2) Output C2 (C3) Output C3 (C2) Output C2 (C3) :
Undefined Sampling C1 (C1) Output C1 (C1) Output C3 (C2) Output C1 (C1) Output C3 (C2) :
Undefined Sampling C2 (C3) Output C2 (C3) Output C1 (C1) Output C2 (C3) Output C1 (C1) :
Undefined Sampling C3 (C2) Output C3 (C2) Output C2 (C3) Output C3 (C2) Output C2 (C3) :
Undefined Sampling C1 (C1) Output C1 (C1) Output C3 (C2) Output C1 (C1) Output C3 (C2) :
Remark ( ) indicates the case of left shift. Figure 5-5. Pixel Arrangement of Double-Side Delta Array and Multiplexer Operation -
R B G C1 C2 C3
PD16782 S1
Right shift (R,/L = "H"), MP/TH = "H", MP/1.5 = "H" S2 S3 S4
R B R G
B R B
G B G
R G R
B R B
G B G
R G R
R B G
B R
G B
R G
B R
G B
R G
S300 G R B C1 C2 C3 PD16782
S299
S298
S297
Left shift (R,/L = "L"), MP/TH = "H", MP/1.5 = "H"
Data Sheet S15806EJ1V0DS
13
PD16782
Figure 5-6. Timing Chart of Both-Sides Delta Array -
RESET INH S1 (S300) Sampling input data Output S2 (S299) Sampling input data Output S3 (S298) Sampling inputdata Output undifined
undifined
C2 (C3)
undifined
C1 (C1) C2 (C3)
C2 (C3) C1 (C1)
C1 (C1) C2 (C3) C1 (C1)
undifined
undifined
undifined
C3 (C2)
undifined
C2 (C3) C3 (C2)
C3(C2) C2 (C3)
C2 (C3) C3 (C2) C2 (C3)
undifined
undifined
undifined
C1 (C1)
undifined
C3 (C2) C1(C1)
C1 (C1) C3 (C2)
C3 (C2) C1 (C1) C3 (C2)
undifined
S299 (S2) Sampling input data Output S300 (S1) Sampling input data Output
undifined
undifined
C3 (C2)
undifined
C2 (C3) C3 (C2)
C3 (C2) C2 (C3)
C2 (C3) C3 (C2) C2 (C3)
undifined
undifined
undifined
C1 (C1)
undifined
C3 (C2) C1 (C1)
C1 (C1) C3 (C2)
C3 (C2) C1 (C1) C3 (C2)
undifined
14
Data Sheet S15806EJ1V0DS
PD16782
5.1.4 Mosaic array mode (MP/TH = H, MP/1.5 = L) Table 5-4. Relation between Video Signals C1 to C3, and Output Pins -
Line No. (number of INHs) 0 1 2 3 4 5 : RESET INH S1 to S300 S2 to S299 S3 to S298 S4 to S297 ... ... ... ... ... ... ... ... S299 to S2 S300 to S1
H L L L L L :
L :
Undefined Sampling C1 (C3) Output C1 (C3) Output C3 (C2) Output C2 (C1) Output C1 (C3) :
Undefined Sampling C2 (C2) Output C2 (C2) Output C1 (C1) Output C3 (C3) Output C2 (C2) :
Undefined Sampling C3 (C1) Output C3 (C1) Output C2 (C3) Output C1 (C2) Output C3 (C1) :
Undefined Sampling C1 (C3) Output C1 (C3) Output C3 (C2) Output C2 (C1) Output C1 (C3) :
Undefined Sampling C2 (C2) Output C2 (C2) Output C1 (C1) Output C3 (C3) Output C2 (C2) :
Undefined Sampling C3 (C1) Output C3 (C1) Output C2 (C3) Output C1 (C2) Output C3 (C1) :
Remark ( ) indicates the case of left shift. Figure 5-7. Pixel Arrangement of Mosaic Array and Multiplexer Operation -
R G B C1 C2 C3
PD16782 S1 S2
Right shift (R,/L = "H"), MP/TH = "H", MP/1.5 = "L" S3 S4 S5 S6 S7
R B G R B
G R B G R
B G R B G
R B G R B
G R B G R
B G R B G
R B G R B
Data Sheet S15806EJ1V0DS
15
PD16782
Figure 5-8. Timing Chart of Mosaic Array -
RESET INH S1 (S300) Sampling input data Output S2 (S299) Sampling input data Output S3 (S298) Sampling inputdata Output undifined
undifined
C1 (C3)
undifined
C3 (C2) C1 (C3)
C2 (C1) C3 (C2)
C1 (C3) C2 (C1) C1 (C3)
undifined
undifined
undifined
C2 (C2)
undifined
C1 (C1) C2 (C2)
C3(C3) C1 (C1)
C2 (C2) C3 (C3) C2 (C2)
undifined
undifined
undifined
C3 (C1)
undifined
C2 (C3) C3(C1)
C1 (C2) C2 (C3)
C3 (C1) C1 (C2) C3 (C1)
undifined
S299 (S2) Sampling input data Output S300 (S1) Sampling input data Output
undifined
undifined
C2 (C2)
undifined
C1 (C1) C2 (C2)
C3 (C3) C1 (C1)
C2 (C2) C3 (C3) C2 (C2)
undifined
undifined
undifined
C3 (C1)
undifined
C2 (C3) C3 (C1)
C1 (C2) C2 (C3)
C3 (C1) C1 (C2) C3 (C1)
undifined
16
Data Sheet S15806EJ1V0DS
PD16782
5.1.5 Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn (1) Simultaneous sampling ( ( ) indicates the case of left shift.)
CLI1 STHR (STHL) SHP1 (SHP300) SHP2 (SHP299) SHP3 (SHP298) SHP4 (SHP297) SHP5 (SHP296) SHP6 (SHP295) C1 sampling C2 sampling C3 sampling C1 sampling C2 sampling C3 sampling
Remark C1 through C3 are sampled while SHPn is high level. (2) Successive sampling ( ( ) indicates the case of left shift.)
CLI1 CLI2 CLI3 STHR (STHL) SHP1 (SHP300) SHP2 (SHP299) SHP3 (SHP298) SHP4 (SHP297) SHP5 (SHP296) SHP6 (SHP295) C1 sampling C2 samling C3 sampling C1 sampling C2 sampling C3 sampling 3-phase clock
Remarks 1. Input a three-phase clock to shift clock pins CLI1 through CLI3. 2. The video signals (C1 to C3) are sampled while SHPn is high level.
Data Sheet S15806EJ1V0DS
17
PD16782
5.2 Sample and Hold Circuit The sample and hold circuit samples and holds the video input signals C1 through C3 selected by the multiplexer circuit in the timing shown below. Swa1 through Swb2 are reset by the RESET signal and change at the rising and falling edges of the INH signal (refer to 1. BLOCK DIAGRAM.).
RESET
Data undifined INH Swa1 Swa2 Swb1 Swb2
undifined
ON
ON
5.3 Write Operation Timing The sampled video signals are written to the LCD panel by output currents IVOL and IVOH via output buffer. The dynamic range is 4.3 V MIN. (VDD2 = 5.0 V). While INH = H, do not stop shift clocks CLI1 through CLI3. The output operation of this IC is controlled by INH signals. INH = Hi-Z INH = Connected with internal circuit (switch sample and hold circuit at the falling edge.) Therefore, performing VCOM inversion while INH = L causes current flow to these IC output pins, which may result in malfunction. Perform VCOM in version during INH = H (Hi-Z) and start output operation of the next line after the VCOM signal is stable enough to operate. Make sure to evaluate this output operation sufficiently.
18
Data Sheet S15806EJ1V0DS
PD16782
Cautions 1. Turn on power to VDD1, logic input, VDD2, and video signal input in that order to prevent destruction due to latch-up, and turn off power in the reverse sequence. Observe this power sequence even during the transition period. 2. The PD16782 is designed to input successive signals such as chrome signals. The input band of the video signals is designed to be 9 MHz MAX. If video signals faster than that are input, display is not performed correctly. 3. 4. 5. 6. Insert a bypass capacitor of 0.1 F between VDD1 and VSS1 and between VDD2 and VSS2. If the power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage fluctuates. Display may not be correctly performed if noise is superimposed on the start pulse pin. Therefore, be sure to input a reset signal during the vertical blanking period. Even if the start pulse width is extended by half a clock or more, sampling start timing SHP1 is not affected, and the sampling operation is performed normally. When the multiplexer circuit is used in the vertical stripe mode, C1 to C3 are simultaneously sampled at the rising edge of SHPn. Internally, however, only CLI1 is valid. Therefore, input a shift clock to CLI1 only. At this time, keep the CLI2 and CLI3 pins to "L". When using the multiplexer circuit in the delta array mode or mosaic array mode, C1 to C3 are sequentially sampled. Input a three-phase clock to CLI1 through CLI3 (for the sampling timing, refer to 2. FUNCTIONAL DESCRIPTION.). 7. The recommended timing of tR-1 and PWRES on starting is shown below (The following timing chart shows simultaneous sampling.). An INH pulse width of at least 5 clocks is required to reset the internal logic. Unless the INH pulse is input after reset, sampling is not performed in the correct sequence.
CLI1 1 PWRES RESET tISETUP tR-I INH 3 clocks MIN. STHR (STHL) tIHOLD PWINH: 5 clocks MIN. 2 3 4 5 1 2 3
SHP1 to SHP 3 SHP4 to SHP6 SHP7 to SHP 9
Data Sheet S15806EJ1V0DS
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PD16782
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS1 = 0 V)
Parameter Logic supply voltage Driver supply voltage Logic input voltage Video input voltage Logic output voltage Driver output voltage Driver output current Operating ambient temperature Storage temperature Symbol VDD1 VDD2 VI VVI V01 V02 IO2 TA Tstg C1 to C3 Condition Ratings -0.5 to +6.0 -0.5 to +6.0 -0.5 to VDD1 +0.5 -0.5 to VDD2 +0.5 -0.5 to VDD1 +0.5 -0.5 to VDD2 +0.5 10 -30 to +85 -65 to +125 Unit V V V V V V mA C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = -40 to +85C, VSS1 = VSS2 = 0 V)
Parameter Logic supply voltage Driver supply voltage Video input voltage Driver output voltage High level Input voltage Low level Input voltage Symbol VDD1 VDD2 VVI V02 VIH VIL Condition MIN. 3.0 4.5 VSS2 + 0.35 VSS2 + 0.35 0.7 VDD1 0 TYP. 3.3 5.0 MAX. 5.5 5.5 VDD2 - 0.35 VDD2 - 0.35 VDD1 0.3 VDD1 Unit V V V V V V
20
Data Sheet S15806EJ1V0DS
PD16782
Electrical Characteristics (TA = -30 to +85 C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Maximum video signal output voltage Minimum video signal output voltage Logic high level output voltage Logic low level output voltage Video signal high level output current Video signal low level output current Reference voltage 1 Reference voltage 2 Reference voltage 3 Output voltage deviation 1 Output voltage deviation 2 Output voltage deviation 3 Logic input leakage current Video input leakage current Logic dynamic current consumption Symbol VVOH VVOL VLOH VLOL IVOH IVOL VREF1 VREF2 VREF3 VVO1 VVO2 VVO3 ILL IVL IDD1 fCLI = 14 MHz VVI = 2.0 V, no load, fINH = 15.4 kHz, PWINH = 5.0 s Driver dynamic current consumption IDD2 fCLI = 14 MHz VVI = 2.0 V, no load, fINH = 15.4 kHz, PWINH = 5.0 s 12 mA VDD1 = 5.0 0.5 V 4.5 mA VDD1 = 3.3 0.3 V STHL, STHR pins, IOH = -1.0 mA STHL, STHR pins IOL = 1.0 mA INH = L, VOF = VDD2 - 1.0 V VO = VDD2 - 0.5 V INH = L, VOF = 1.0 V, VO = 0.5 V VDD2 = 5.0 V, TA = 25C, VVI = 0.5 V VDD2 = 5.0 V, TA = 25C, VVI = 2.0 V VDD2 = 5.0 V, TA = 25C, VVI = 3.5 V VDD2 = 5.0 V, TA = 25C, VVI = 0.5 V VDD2 = 5.0 V, TA = 25C, VVI = 2.0 V VDD2 = 5.0 V, TA = 25C, VVI = 3.5 V Logic input except Osel Osel, VI = VDD = 3.3 V 90 10 3 1.0 30 mV 30 mV 30 mV 3.49 V 1.99 V 0.49 V 0.08 0.20 mA -0.20 -0.08 mA 0.1 VDD1 V 0.9 VDD1 Condition MIN. VDD2 - 0.35 0.35 TYP. MAX. Unit V V V
A A A
mA
Remarks 1. VOF: output applied voltage, VO: output voltage without load 2. The reference values are typical values only. The output deviation is only guaranteed within the chip.
Data Sheet S15806EJ1V0DS
21
PD16782
Switching Characteristics (TA = -30 to +85C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Start pulse propagation delay time Clock frequency 1 Clock frequency 2 Logic input capacitance STHL, STHR input capacitance Video input capacitance Symbol tPHL tPLH fCLK 1 fCLK 2 CI1 CI2 C3 With 3-phase clock input Other than STHL, STHR STHL, STHR C1 to C3, VVI = 2.0 V Condition CL = 20 pF CL = 20 pF MIN. 10 10 TYP. MAX. 54 54 15 8 15 20 50 Unit ns ns MHz MHz pF pF pF
Timing Requirements (TA = -30 to +85 C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Clock pulse width Start pulse setup time Start pulse hold time Reset pulse width INH setup time INH hold time Reset-INH time INH pulse width Symbol PWCLI tSETUP tHOLD PWRES tISETUP tIHOLD tR-I PWINH Condition Duty = 50% MIN. 33 8 8 66 33 33 81 5 TYP. MAX. Unit ns ns ns ns ns ns ns CLK
Remark Keep the rise and fall times of the logic input signals to within tr = tf = 5 ns (10 to 90%). As an example, the switching characteristic wave of CLI1 is defined on the next page.
22
Data Sheet S15806EJ1V0DS
PD16782
Switching Characteristic Waveform (Simultaneous/successive sampling) Start Pulse Input Timing
1/fCLI1 PWCLI1 PWCLI1 VDD1 CLI1 50% 50% VSS1 tSETUP tHOLD VDD1 STHR (STHL) 50% 50% VSS1
VDD1 SHP1 (SHP300) VSS1
Start Pulse Output Timing
VDD1 50% 50% VSS1 tPLH tPHL VOH STHL (STHR) 50% 50% VOL
CLI1
Remark The input/output timing of the start pulse is the same for simultaneous/successive sampling.
Data Sheet S15806EJ1V0DS
23
PD16782
RESET INH Pulse Timing
CLI1
50%
PWRES
RESET
50%
50%
tISETUP
INH
tIIHOLD
50%
50%
tR-I
PWINH
24
Data Sheet S15806EJ1V0DS
PD16782
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S15806EJ1V0DS
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PD16782
Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E)
* The information in this document is current as of December, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics's willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11

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